1. Field of the Invention
The disclosure relates to a method for forming a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2011-015139, filed Jan. 27, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
The dual-damascene method, whereby an interconnect and a contact plug are formed simultaneously, has been used as a method for manufacturing a semiconductor device in the related art.
In the dual-damascene method, first a first interlayer insulating film, an etching stopper film, and a second interlayer insulating film are sequentially laminated over an interconnect. Next, a contact hole is formed that passes through the first interlayer insulating film, the etching stopper film, and the second interlayer insulating film, and that also exposes the upper surface of the interconnect.
Next, an interconnect formation trench is formed integrally with the contact hole on the second interlayer insulating film. Then, a barrier layer is formed that covers the inner surface of the contact hole and the interconnect formation trench, after which a metal such as copper (Cu) or the like is buried into the contact hole and the interconnect formation trench, so as to form the interconnect and the contact plug simultaneously.
In the above-noted dual-damascene method, it is preferable that the contact hole be formed first and then the interconnect formation trench be formed, using the via-first method. These are disclosed in Japanese Patent Application Publication No. JPA 2007-134717.